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Hi,
One of the verilog modules has the line:
input int;
When running Verilog::Netlist -> read_file() the following message is generated:
%Error: soc.v:3282870: syntax error, unexpected "integer", expecting "IDENTIFIER"
This seems to me a syntactically correct verilog declaration. I don't mind getting a warning, but after this my script aborts. How can I avoid or bypass this so the script continues.
Thanks.
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