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CPAN Forum - Verilog-Perl
This section of the site is for discussing the Verilog-Perl CPAN distribution.
All the posts related to modules of WSNYDER.
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| Title | Thread | Date | Posted by |
|---|---|---|---|
| Re: *DO NOT POST HERE* | (+1) | 2009-09-30 16:08:23-07 | wsnyder |
| *DO NOT POST HERE* | (+1) | 2009-09-30 16:06:51-07 | wsnyder |
| input int; | 2008-10-27 07:32:11-07 | avshae | |
| A few proposed changes to Verilog::Netlist | 2008-08-14 20:19:58-07 | mcorazao | |
| Verilog::SigParaser does not take prepocessed output | 2007-10-18 11:35:26-07 | dbsingh1880 | |
| Re: How to use read_libraries to resolve the reference? | (+1) | 2007-07-12 01:31:01-07 | walter |
| escaped names termined with whitespace | 2007-07-11 22:38:56-07 | chinnery | |
| How can I get at a parameter defined in a module from the data structure ? | 2007-06-27 12:59:37-07 | berke | |
| How could I write out my new cell or module? | 2007-06-12 03:16:05-07 | walter | |
| How to use read_libraries to resolve the reference? | 2006-12-27 10:03:22-08 | guc | |
| How to use read_libraries to resolve the reference? | (+1) | 2006-12-27 09:24:20-08 | guc |
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